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Old August 23rd, 2007, 09:55 PM   #1
freecableguy
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Improved Memory Scaling: The Natural Progression of Technology

I woke this morning and within a few minutes sat down to my laptop to glance through the morning's email and perhaps reply to a few as time permited. An IM chat window blinked in the toolbar - I decided to bite. A friend who works for one of the major review sites (no need to name names) had a few questions and I was all too happy to give my input. We chatted for a few minutes about UMPR ratings for DDR2/DDR3 memory, which was created right here at The Tech Repository and introduced in our most recent article. The exacting details of the conversation are quite inconsequential, what I want to talk about is a little realization that didn't really come to me until about an hour later as I sat at my desk sipping my $4 latte.

The reviewer noted that, for the most part, all the memory included in his upcoming review scaled "much better" at CAS 5 than CAS 4 and CAS 3. This seems harmless enough but there's a lot of truth to this I decided and I want to take just a few minutes to outline my thoughts. You see, theres a perfectly good explaination as to why all memory scales better at ever increase CAS settings. Simply put, as CAS is increased the change in true latency (expressed in nanoseconds, which can be calculated easily using the equation to the left side of the arrow below) per change in memory frequency step increase becomes smaller. Even more simply put, as CAS is increased you can increase memory frequency by an ever increasing range before reaching your memory's latency minimum, or limit.

The second equation, to the right of arrow, is nothing more than the derivative of the equation to the left. If you don't believe me open any calculus book you have laying around (or better yet Google it - remember, you can't believe everything you read on the Internet) and check it out for yourself. Why do I bring this up? One reason really, while the nanosecond (ns) per megahurtz (MHz) average shown in the table below is good, it's just that - an average. This second equation will allow you to calculate the instantaneous change in CAS latency at any single CAS setting/memory frequency pair - the derivative if you will. For example, CAS latency at 800MHz/CAS 3 would be 3*2000/800 = 7.5 ns. And the ns/MHz would be -3*2000/800^2 = ~-0.0094 ns/Mhz...yep, small. You should note though that this value is below the average of ~-0.0088 ns/MHz. I'll bet you'll find that the same calculation for, say 850MHz, is above the average....funny how averages work.


For those that have familiarized themselves with the concept of the CALWI (CAS Access Latency Window of Interest) - take for example a CALWI of 7.0 to 7.5 ns - the higher the CAS value the larger the frequency range between these two bounds. The short table below details just this concept. In each case the CALWI is held constant. We'll look a just a few CAS settings, 3, 4 and 5 (I'll leave it as an exercise to you to continue into higher ranges...and DDR3 territory).

The first thing you may note is that the "Size of Memory Frequency Window" column contains sucessively increasing window ranges. Not surprisingly the column to the right shows that as CAS is increased that the step change in latency (ns) per memory frequency (MHz) increase becomes smaller. There are a few easy ways to calculate this: 1) Divide the total change in latency, the range defined by the CALWI, by the memory frequency window, or 2) Calculate each step change and average them all together. Guess which one's easier? Excel makes short work of this in either case. You can see now why it makes sense that the "ns/MHz" step size become smaller as the memory window becomes larger - any time you divide a number by an increasingly larger number the resultant is increasingly smaller.




You should also come to the realization that as long as memory speeds continue to increase, requiring ever increasing CAS settings in order to maintain similiar true CAS latencies, that this trend will be move along indefinately. In the end this is actually a good thing. Smaller step increases means more percise tuning. A corollary to this is the CPU multiplier, which happens to work in the opposite manner. In that case the CPU multipier is a range of fixed integer values and the step change (the default to OC FSB limit) just seem to get higher and higher. This makes fine-tuning CPU speed difficult as small multipliers and large FSBs means that the change between 7x and 8x at 500MHz FSB can be so large as to prevent full utilization of available memory performance capability that might otherwise be achievable. (There are two partial solutions to this. The first is memory dividers (ratios). The second, which is about due, is half multipliers.)

In order to provide an easy means for comparison I have normalized the ratio of nanosecond (ns) to megahurtz (MHz) change. If CAS 3 is 1.00 then you can see that CAS 4 step changes are only 0.75 (or 75% that of CAS 3 step changes) as large and CAS 5 step changes are 0.60 (60%).

And finally, the data that really matters - the increase in the size of the potential memory frequency window - the "scalability" if you will. Although many of the numbers calculated are not need in order to arrive at this conculsion, I feel they are appropriate as they can only help to explain this phenomenon. The "Percent Increase in Frequency Window Size" is undoutably valuable to know. Nothing for the CAS 3 setting (as this is our baseline, and the point from which other windows are compared), a 33% increase for CAS 4 and a whopping 67% increase for CAS 5. Care to guess what happens at CAS 6? Just another reason why DDR3 is going to be good.

That's all for me for right now. As always, you can always drop me a line if you want to chat. I suggest you register and send me PM though as my tech repository email address receives too much spam for me to cope (thanks, CES 2007 registration).


-FCG
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