|October 8th, 2006, 06:03 PM||#1|
Old Jedi master
Join Date: Sep 2006
Location: Manchester, UK
Secrets of the i965 based Asus P5B and chipset strap uncovered.
This is just the start, as I find more I will add to this post.
Tests conducted with 6400 Allendale good to 510fsb using the 7 multi.
OCZ micron IC based dimms (generic ES samples) No fixed product name or SPD
OCZ 600W Evo stream PSU
First tests were to determine how Asus unlocked the board to reach 500+fsb.
From my chipset strap guide we all know that around 370fsb Intels 975/965 chipset starts to have issues if its left on the 1067 strap. Now the fact this 965 based board is doing 500fsb+ means somewhere along the line Asus force a strap change in bios, this means somewhere between 370 and 500+FSB the board loses memory performance.
So I conducted a few easy tests, first graph shows the theory behind how Asus are manipulating the straps without you knowing.
From the graph the blue section shows how the strap should effect the clock on the Northbridge. From 267 fsb (1067 strap) the NB clock rises until 333fsb(1333 strap) where it falls back to default and starts to ramp again as it moves closer to 400fsb (1600 strap if it existed) then it resets again as the fsb moves to 467fsb (1867strap if it existed) Now this all depends on the strap settings being set as they should be, fact is they are not.
So, we then look at the red section of the graph which shows the NB clock rising from 267fsb all the way to 400fsb, this means that Asus has a massive overclock on the northbridge before they reset the strap at 401fsb. Now they have not utilised the 1600 strap as far as we know; at this time it is not known to exist, so the boards sets the 1333 strap. This means the NB instead of completely resetting to its base clock frequency actually resets in an already overclocked state as the reset point was actually 333fsb, but the CPU fsb is already at 401; infact it resets to what should be its max overclock if the straps were actually being set correctly.
From this point the internal latency on the chipset losens even though the chipset its self is overclocked. This allows the chipset clock to ramp up even higher than it did under the 1067 strap. Now the red section of the graph shows what would happen if the straps were reset at the correct strap points if Asus continued the trend of strap manipulation and if the 1600 and 1867 straps were available...issue is they don't seem to be, so we have to now look at the green section of the graph to show what is actually happening on the board.
From the green section we see the NB clock ramps up with the CPU fsb from 267(1067 strap) all the way to 400fsb, where some manipulation occurs, and the board sets the 1333 strap but from a base 400CPU fsb. The NB clock then dips down to around 467fsb; where upon its clock rises higher than was possible on the 1067 strap. From 467fsb the NB is running it's highest internal clock frequency even though it has the slackest latency setting. The increase of clock speed has a positive effect on memory performance bringing it into line with what you see at the highest point NB clock on the 1067 strap, however the cpu is now running much faster than was previously possible under the 1067 strap.
This graph actually shows memory performance compared to actual CPU bus speed set with 4-4-4- timings 1:1. As you see there is a marked dip in memory performance at 400fsb where the chipset clock speed dips, infact you have to go back to 360fsb/1067 strap to see the same performance from the dimms which shows the 1067 strap is MUCH faster than the 1333 on this motherboard. Now the graph is quite linear and around 470fsb you see memory performace now matches whats is seen at the top end of the 1067 strap, the only issue is it is now stable where under the 1067 strap at 399fsb you probably will see some instability issues. From 467fsb onwards you will now see the highest performace from your dimms although you are relying on how good the NB overclocks under the 1333 strap.
Now what I did not show on this latest graph is that from 360fsb to 399fsb the memory was VERY unstable, infact scrolling errors in memtest were the norm in all tests, not just test 5. This proves under the 1067 strap the 965 chipset is hitting the same clock speed limitations as the 975 chipset, the only difference is the board actually still tries to run, on all the 975 boards i have tested once the chipset hits its max clock the boards just give up.
One other thing is 400fsb has an added tweak. 399fsb had memtest bandwidth of 4799MB's but was completely unstable, 400fsb had bandwidth of 4812MB/s and was completely stable... but as soon as I moved to 401fsb bandwidth shot down to 4324MB/s.
This situation reminds me of the old P4P800 turbo mode at 200fsb where Asus forced PAT and a latency change on the chipset to make the boards look good for reviews. I have a feeling the 1333 strap is forced at 400fsb but the latency we see at 1067 strap is still in play maybe...so it may be worth setting 400fsb, boot to windows and clock higher with clockgen for benchmark runs with this board
To finish...if you are clocking 1:1 I seriously suggest you skip 360 to 400fsb and push up from 401, the errors you see are NB related and not the memory in most cases.
That is it for the first installment...stay tuned for more.
|October 8th, 2006, 06:11 PM||#2|
Further investigation into this topic has revealed some rather interesting conclusions and also a few new theories. The "classicial" understanding of North Bridge (NB)/Memory Controller Hub (MCH) overclocking has always lead us to believe that the CPU multiplier had nothing to do with the North Bridge Core Clock (NBCC). Not so with the 965 chipset. I suspect a lot of this same information to be true for 865/875/975 but I cannot test at this time as I don't have any other boards readily available.
Here's what I mean...
How we normally calculate CPU Core Clock:
Example: Multiplier of 10x with a FSB of 266MHz yields a CPU core speed of 2.66GHz
Here's how we would now calculate the North Bridge Core Clock (NBCC):
Example: An Intel E6400 @ 7x500Mhz = 3.5GHz
NBCC = (8/7) * 500 = 571MHz
Since the E6400 has a default multiplier of 8x (8x266 = 2.13GHz) was can see that simply dropping the multiplier to 7x has in effect overclocked the NB!
Note 1: The "Rated FSB" of 4*500 = 2GHz is simply an "marketing effective" way of saying that the Front Side Bus is "quad-pumped" meaning that there are 4 separate 64-bit wide data paths from the CPU to the MCH. Realize that whether you look at it like a single 64-bit pathway running at 2GHz or 4 seperate 64-bit pathways running at 500Mhz it makes no difference in the maximum amount of theoretical data transfer possible per clock cycle.
Note 2: This provided example is dependent on the CPU's default multiplier, therefore an E6600 or E6700, etc. will all scale the NBCC differently...
The NB sets it's internal operating frequency (NBCC) based on the multiplier as set by the BIOS. Rather than set a static value (say, 266MHz) the NB in essence "back calculates" the operating frequency by dividing the CPU core speed by the current set multiplier. Normally, this always yields a stock speed of 266MHz since 266 multiplied by any particular CPU's default multiplier then divided by that same multiplier would always yield the same number....266! Not so when you change the multiplier though!
This helps tremendously to explain why some users reach an "FSB wall" sooner than other and why to this point there seems to have be no explaination as to why someone with an E6400 finds he can reach a higher FSB than someone with an E6600.
Here's what I mean by that:
E6600 @ 7x500 = 3.5GHz
NBCC = (9/7)*500 = 642MHz <- this NBCC may be unachievable by the NB which would artifically create what would be misdiagnosed as an "FSB wall"...
E6400 @ 7x500 = 3.5GHz
NBCC = (8/7)*500 = 571MHz
What we see here is rather interesting....in this case the E6400 CPU may easily reach the outstanding speed of 3.5Ghz, run memory 1:1 @ DDR-1000 AND achieve an amazing NBCC of 571MHz (overclocked from 266Mhz...an eye-popping ~115% increase!) while the user of the E6600 processor, using otherwise identical components, may find that he cannot reach equivalent FSB speeds. The only difference you ask? The default multiplier....
Here's what SANDRA has to say; from what I have seen the only program the happens to report the true NBCC and not just the FSB...
These first two screen shots show how simply changing the multiplier from 8x to 7x overclocks the NB. In this example an increase from (8/8)*400MHz = 400 to (8/7)*400 = 457MHz.
In this screen shot we can see how the NB can easily overcome the "600 FSB" barrier. In this example we prove that the system could run at 600 FSB if two additional conditions can be met, 1) the memory is capable of running at DDR-1200, and 2) the CPU is capable of running at 7x600 = 4.2GHz.
Remember, simply dropping the multiplier to 6x so that we can remove condition #2 from the equation and force the CPU to 6x600 = 3.6GHz would increase the NBCC to (8/6)*600 = 800MHz! *good luck*
Here we can see some of the real potential of the 965 Express chipset. 640MHz on the NB is pretty damn impressive, especially considering this MB is still unmodified.
What have we learned? #1: If you're looking to set FSB WR's you need to use a CPU with a low default multiplier so that you can focus on raising the FSB to sky-high values without sending you NBCC through the roof (preventing failure to POST) since you are mostly likely going to want to use a multiplier that doesn't limit you early by reaching maximum speed (7x, 6x, etc.) The E6300 is looking better by the day....
There's a lot more out there to learn. We are making progress by the day. I will be working with Tony to fit this all together with his above information. NB straps, internal latencies and FSB will soon start to play a major role in our overclocking adventures... :thumbs:
|November 2nd, 2006, 03:49 PM||#3|
Old Jedi master
Join Date: Sep 2006
Location: Manchester, UK
You have to love reverse engineering
6 hrs reading forum posts, white papers etc and I think I found a little more info.
From 2cpu.com this post by XeonTux we see a gem of info from a clockgen white paper, its for 771 CPU's but we all know they are REAL closely related .
Clock generators recieve BSEL signals from the CPU so they set the correct FSB for the CPU its self, from the above table (compiled from various whitepapers and clockgen specs) we see 333(1333) and 400(1600) are listed. Looking at how the Asus P5B is performing could Asus just be switching in 400strap at 400fsb with a latency tweak? I am beginning to think they may be and we are testing to see if the 400 Strap actually works.
i975 on the other hand is not clocking anywhere near as high, I think the main reason is no 400 strap support! 333 gets you close as seen on badaxe1 where some boards do get real close to 500fsb but they are not clocking anywhere near the 550 > 600 that good i965 boards are doing.Here is what the chipset registers will look like.
Just remove the 1600 strap setting for i975 as this is older tech.
More to come soon, for now i feel this is how i965 is clocking better than i975, we all thought it was 1333 strap where in reality it looks like it may be the 1600 strap after all.
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