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Old February 16th, 2007, 03:14 PM   #1
freecableguy
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Lightbulb Intel Processor Power Delivery Design Guidelines and Specifications: Vdroop Explained

Intel Processor Power Delivery Design
Guidelines and Specifications: Vdroop Explained


Date: 19 February, 2007
Author: Kristopher Boughton

Category: Overclocking
Manufacturer: Intel



Introduction to Power Regulation

Allowable tolerances are a necessity in any engineering discipline. Set them too tight and you will find that the combination of component values, manufacturing uncertainties and design margins create a situation in which products never meet validation criteria. Set them too loose and performance may suffer. In either case, the designer(s) must take into account a myriad of variables, some which may be totally transparent to the consumer. Suitability and adaptability criteria, technical specifications, adherence to manufacturing certifications (RoHS, ISO9000, etc.), availability of quality assurance data and feasibility studies, procurement/shipping deadlines, and total cost must all be taken into account. Often times consumers have no idea of the staggering amount of time and resource it takes to sufficiently develop and test a design before release. Re-spins and re-works are relatively cheap when still in the development phase; but expenses can become overwhelming when dealing with a release-to-manufacture (RTM) product. What does all of this have to do with power regulation circuits? The short answer, as we shall see, is everything.

Down to point! This article attempts to explain the basic functionality of the power delivery circuit necessary to support current-generation Intel processors' core (Vcc) power delivery requirements as well as define the principle modes of operation to include design features of DC-to-DC regulators, which convert the input supply voltage to a processor-consumable Vcc voltage. Vcc regulator design for a specific motherboard must meet the specifications of all processors supported by that board in order to guarantee satisfactory performance. Likewise, operation of a processor outside of design specification places an increased burden on the power delivery solution that may result in instability and unreliable operation.

Unlike power supplies (PSUs) which are used to rectify 120VAC (or 220-240VAC if you happen to live in the UK/EU or Australia) mains power to the 3.3v, 5v, and 12v DC (amongst other) voltages used in current-generation systems, the Pulse Width Modulation Integrated Circuit (PWMIC) found on a motherboard is a true step-down DC-DC converter. Meaning that a high-voltage DC supply line is regulated down to the required Vcc (or processor core voltage) using a high-frequency switching PWM circuit. Figure 1 shows the component diagram of the typical Voltage Regulator Down (VRD) configuration. The installed processor provides an 8-bit VID code to the VRD which is decoded and used to set the programmed output voltage. A single multi-phase PWM controller, provided with per-channel current sense data, and voltage sense readings is used to command a bank of synchronous buck converter processor core supply power switching regulators (some recent designs have integrated the functions of these regulators into the controller thereby reducing the need for additional external parts - optimizing for cost and space savings). These regulators then provide signal drive current as required to gate on and off metal oxide field effect transistors (MOSFETs) at a specified switching frequency (usually programmable in the ~1kHz to 1MHz range) as required to develop and maintain the specified Vcc voltage during transient response periods and all processor loading conditions.




Each phase requires one switching regulator, at least two MOSFETs, and a few other associated support components (mainly inductors and capacitors). Although the proper selection of these component values is beyond the scope of this article, the axiom - "bigger is always better" is certainly not true in this instance. For example, the addition of extra capacitors, the favorite VR circuit modification of the over-zealous albeit misguided basement-hobbyest, often does more harm than good. Understanding why there are those that attempt to make these changes isn't hard to do considering all the recent (actually, rather historic) negative publicity surrounding the dreaded "Vdroop problem" that seems to be prevalent in today's motherboards. We're here to tell you that you're much better off learning why Vdroop exists (and why it's needed), rather than attempting to hack up your expensive, well-engineered motherboard in a horrific effort to "correct" the problem.


Design Specifications and Engineering Decisions

Microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. Designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multi-phase converters can accomplish nowadays. Note that the number of phases utilized is left to the discretion of the designer(s) - no VRD configuration includes this specification. The consensus amongst most enthusiasts is that a greater phase count results in a more "stable" Vcore (Vcc) delivery - a fallacy which motherboard designers and industry marketing leaders are all too willing to promote (it's much cheaper to slap a few more power delivery phases on a motherboard than to create an actual high-performance design). Quality of power regulation is dependent on the robustness of the design, to include proper power and ground plane placement, effective signal routing and decoupling measures, selection, location and rated capacity of correctly matched components and overall adherence to sound engineering principles. Because of this, the design and implementation of a well developed 5-phase solution will, in most situations, out perform a "lesser tuned" 8-phase solution.




The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. For example, in a 5-phase converter, each channel switches 1/5 cycle after the previous channel and 1/5 cycle before the following channel. As a result, when summed, the 5-phase converter has a combined ripple frequency five times greater than the ripple frequency of any one phase. Additionally, the peak-to-peak amplitude (see Equation 1) of the combined inductor currents is reduced in proportion to the number of phases. Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance (L) and lower total output capacitance (C) for any performance specification, allowing the designer to use fewer or less costly output capacitors. By this account it is clear why motherboard design companies favor more phases over fewer - but does this really benefit the end user?

Figure 2 illustrates the logic and timings signals developed in response to processor current requirements. Each PWM output state is driven by the difference between the error amplifier output signal and the current correction signal of each phase. At the beginning of each PWM time interval, this signal is compared to an internal modulator waveform and if the sense voltage is lower then the modulator waveform voltage, the PWM signal is commanded low (OFF). A signal is then sent to the appropriate MOSFET driver, which detects the low state of the PWM signal and turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the signal voltage crosses the modulator ramp, the PWM output transitions high - turning off the lower synchronous MOSFET and turning on the upper MOSFET (commanded high). The PWM signal will remain high until the signal voltage crosses the modulator ramp on any successive cycle sampling period. The current outputs for each channel are summed when supplied to the load, in this case the microprocessor. In a 5-phase design, if each upper MOSFET is capable of conducting a maximum of 30A of current then the total peak current available to the load will be approximately 5 x 30A or ~150A. The inductors in each phase help by storing energy in an electric field which act to resist any sudden changes in current flow, dampening potential current spikes that could otherwise damage the processor. The output capacitors work to supply additional current immediately whenever large, near-instantaneous positive change in loading occurs - ensuring stability.




VCC (Vcore) and Vdroop Explained

Load line droop (or Vdroop) is an inherent part of any Intel power delivery design. A current proportional to the average current of all active channels flows through load line regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value. Equation 2 dictates the value for RFB that should be choosen to satisfy the Intel VRD specification (the source of RLL) based on a) the number of power delivery phases (N) and b) the equivalent series resistance (ESR) of the inductor used, effectively known as DCR.

The first question that may come to mind is why droop voltage at all. Truthfully, in most cases the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load/current demand changes. The magnitude of the spike is proportional to the magnitude of the load swing and the ESR/ESL of the output capacitor(s) selected. By positioning the no-load voltage (VNL) level near the upper specification limit (bound by the Vccmin load line), a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance (RLL), the output voltage under load can be effectively 'level shifted' down so that a larger positive spike can be sustained without crossing the upper specification limit (such as when the system suddenly leaves a heavy load condition). This makes sense as the heavier the CPU loading the smaller the potential negative spike and vice versa for lower CPU loading/positive spikes. The resulting system is one in which the system operation point is bound by Vccmin and Vccmax at all times (although short excursions above Vccmax are allowed by design).





Plotting Vcc while varying Icc from 0A to Iccmax (125A used in this example) establishes the Vccmax, Vcctyp (typical) and Vccmin socket load lines. (Vccmax establishes the maximum DC socket load line boundary while Vccmin establishes the minimum AC and DC voltage boundary.) The results are shown below in Figure 3 along with the equations, taken straight from Intel power delivery design specifications, that were used to develop the table. Figure 4 is a graphical illustration of this data table. This is a good representation of how a power delivery circuit should be designed such that the output voltage droops in proportion to the output current.




Glossary of Definitions:

ICC - Processor current.

RLL - Load line impedance: Defined as the ratio of voltage droop/current step. This is the load line slope. In this document, the load line is referenced at the socket unless otherwise stated.

TOB - Vcc regulation tolerance band: Defines the voltage regulator’s 3-σ voltage variation across temperature, manufacturing variation, and age factors. Must be ensured by design through component selection. Defined at processor maximum current and maximum VID levels.

VCC - Processor core voltage.

VID - Voltage IDentification: A code supplied by the processor that determines the reference output voltage to be delivered to the processor Vcc lands. At zero amperes and the tolerance band at +3-σ, VID is the voltage at the processor.


Accurate Processor Power and Current Determination

Figure 4 helps to graphically illustrate this new, innovative method for for determining CPU power (wattage) and current at any given frequency/voltage combination. Instead of estimating the results based on crude mathematical relationships, the method being introduced makes use of easily measured empirical data and intuitive physical principles. First collecting some initial information at stock settings makes possible the opportunity to accurately calculate processor current and wattage under any and all loading conditions at all times. In fact, by implementing this method as a hardware monitoring routine it is entirely possible for processor current and wattage to be monitored in realtime!

Calculating processor current and wattage is as easy as following Procedure A and Procedure B, shown below. Alternatively, you can download the MS Excel spreadsheet (to be added at a later date) included for easy data entry - results are displayed automatically. An automated utility/tool is also in development, more as it becomes available.




Procedure A - Determining Observed TOB (Offset Voltage):


1 Boot the system at default frequency with Auto VID. Do not overclock at this time.

2 Place the processor under full load (100% CPU usage for all cores) and measure Vcc by probing actual supplied core voltage on the motherboard.

3 Subtract the voltage read in Step 2 from the VID for the installed processor - this is the observed voltage droop (Vdroop). The default VID can be read from the CPU retail box identification label or might possibly be listed by BIOS. Note that the VID is the programmed voltage and not the actual supply voltage.

4 Divide the processor TDP (thermal design power) by the voltage read in Step 2 - this is the processor current (Icc) in amps.

5 Multiply processor current (Step 4) by the VRM load line impedance (RLL). Note: RLL for VR Configuration 04B / 05A / 05B / 06 is 1.0 milliohms. RLL for VR Configuration 04A is 1.4 milliohms. Consult Intel datasheets for RLL for other, older VR configurations.

6 Subtract the results of Step 4 from 1000 times the value determined in Step 3 (observed Vdroop) - this is the observed TOB (mV) for the motherboard/CPU combination used to complete this testing. This value can only be used when working with the CPU and motherboad combination used to produce this particular result - if either component is changed simply repeat this procedure with the new hardware.

The observed TOB should be between zero and twice the default TOB for the VR Configuration used on the motherboard - if not you have either read an incorrect value or made a mathematical error, try again. The observed TOB for this combination of hardware should not change over time, although wear (time-in-life), system temperature, and other external factors not directly compensated for may create slight variations. The best practice would be to calculate the observed TOB before determining values for overclocked systems whenever feasible.

Now that we know the TOB observed value we can easily calculate the offset voltage of the PWM controller by first making a few simple assumptions: a) the digital to analog (DAC) error in the VID decode network is essentially zero, b) the Vcc power delivery circuit behaves like an otherwise ideal design (which can be defined using the typical load line equation), and c) the established offset is defined as being for full load at stock frequencies and default VID. For example, let's assume that our calculated result for Procedure A is 9 mV and default (read: typical) TOB for our platform is 16 mV. That would make the difference 7 mV, in the positive direction (since a 9 mV droop is less than a 16 mV droop). Based on our previously established assumptions this would mean that the design actually included a reduction in droop of 7 mV! This may seem counter-intuitive, especially to those that have spent a lot of time cursing their luck whenever they see any droop at all.


Procedure B - Determining Processor Current/Power:


Note: First complete Procedure A - Determining Observed TOB (Offset Voltage), shown above, before continuing any further.

1 Boot the system at any frequency/voltage combination.

2 Place the processor under full load (100% CPU usage for all cores) and measure Vcc by probing actual supplied core voltage on the motherboard.

3 Subtract the voltage read in Step 2 from the programmed voltage (as selected in BIOS) for the installed processor - this is the observed voltage droop (Vdroop).

4 Subtract the observed TOB (found in Procedure A) from 1000 times the value determined in Step 3 (observed Vdroop).

5 Divide the results of Step 4 by VRM load line impedance (RLL) - this value is the observed processor current for the tested frequency/voltage.

6 Multiply the processor current (Step 5) by the measured Vcc from Step 2 - this is the observed processor power (wattage).

Give this method a shot and see how closely the results correlate to the more traditional power calculation method (defined by Equation 5):



Where Pf is the final power, Po is the initial power (TDP), Vf is the final voltage (as read), Vo is the actual voltage (as read) for default VID, Ff is the final frequency, and Fo is the initial frequency (default processor speed). Units used only need to be consistent (i.e. frequency can be expressed in either MHz or GHz, etc.). Although this method requires the collection of more variable data the end results should be somewhat comparable. We are of the mind to believe that our results are closer to the truth but have no desire to attempt to prove this, at least for now...


References





-FCG

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