How memory frequency affects latency - Tighter timings vs. Higher speeds?

[freecableguy]

CL (CAS latency, or Column Address Strobe latency) is rated/measured in clocks cycles, commonly referred to as ‘ticks.’ Therefore a CAS value of 4 means 4 cycles, which as you may have already surmised, is entirely dependent on memory speed. The higher the speed, the faster the cycle time, meaning that at lower memory speed coupled with a lower CAS value can in fact provide tighter latencies (and often more burst bandwidth) than a solution involving higher memory speeds and “looser” timings.

Why do I bring this up? Simple, the performance community is home to one of the most long standing memory questions ever - what's more important high frequency or tighter timings? Those that believe that processor X will perform better with higher memory speeds and looser timings, and conversely, those that believe that lower memory speeds with tigher timings are best may be surprised by what they find here. In fact, like so many things in this world, the truth lies somewhere in between. I would even be so kind as to say that everyone can rejoice in being partially correct (however, you must also accept that you may also be partially incorrect...).

PC-4200 -> DDR-533 -> 266MHz base frequency
266MHz = 266 million cycles per second -> 3.76 x 10-9 sec per cycle (3.76 ns)

CL 3 = 3 x 3.76 ns = 11.28 ns
CL 4 = 4 x 3.76 ns = 15.04 ns
CL 5 = 5 x 3.76 ns = 18.80 ns

PC-5300 -> DDR-667 -> 333MHz base frequency
333MHz = 333 million cycles per second -> 3.00 x 10-9 sec per cycle (3.00 ns)

CL 3 = 3 x 3.00 ns = 9.00 ns
CL 4 = 4 x 3.00 ns = 12.00 ns
CL 5 = 5 x 3.00 ns = 15.00 ns

Already we can see that CL5 latency with DDR-667 is roughly equivalent to CL4 at DDR-533…we shall continue our documentation…

PC-6400 -> DDR-800 -> 400MHz base frequency
400MHz = 400 million cycles per second -> 2.50 x 10-9 sec per cycle (2.50 ns)

CL 3 = 3 x 2.50 ns = 7.50 ns
CL 4 = 4 x 2.50 ns = 10.00 ns
CL 5 = 5 x 2.50 ns = 12.50 ns
CL 6 = 6 x 2.50 ns = 15.00 ns

Ah ha! CL6 isn’t looking so bad after all…we continue…

PC-8000 -> DDR-1000 -> 500MHz base frequency
500MHz = 500 million cycles per second = 2.00 x 10-9 sec per cycle (2.00 ns)

CL 3 = 3 x 2.00 ns = 6.00 ns
CL 4 = 4 x 2.00 ns = 8.00 ns
CL 5 = 5 x 2.00 ns = 10.00 ns
CL 6 = 6 x 2.00 ns = 12.00 ns

Hmmm…seems DDR-1000 @ CL6 has the equivalent CAS access latency of DDR-667 @ CL4. You may be starting to wonder why everyone is so scared of “loose timings” at higher memory frequencies…yeah, me too.


This graphical illustration may help this point:

EDIT: Updated table for additional DDR3 speeds/latencies (added 8/2/2007)

I've highlighted what I would consider to be the important trend in this graphic. The dark grey boxes correspond to high-performance bins...DDR-800 @ CL3, DDR-1000 @ CL4, etc. The light red boxes are closer to rated speeds for performance memory (often conservatively under estimated) - move one box the right for the particular speed grade in question to see the higher latency. The light green boxes can be best described as the 'ram and jam' settings (one box to the left). Sure DDR-1000 will do CL3....if you want to kill it in a week of 24/7 use.

The second point I would like to make is this: DDR3 is coming. Don't be scared by CL6, CL7 and *gulp* even CL9. If you continue the graph above, extending both into higher speed grades and higher latencies I am confident that you will find that the same trend continues. These "higher" latencies are a necessity in order to maintain the minimum signal sample and hold times required for proper data transfer.

Check back soon for some more discussion on the matter when we'll look at the considerations to be made when deciding where to set your CPU multiplier, NB strap and memory strap (and timings) for maximum performance. Remember, each component has a maximum performance point, unfortunately they can not always be established concurrently. Our goal can only be to pick the best solution based on how you use your system...


-FCG

[Tony]

A rough addition to Kris' table here shows upto where DRR3 is known to clock to at this present time. You have to realise that to see any speed increase you may need to run CAS latency one step lower than the compared CAS latencies running down the table; in some circumstances you may as well run the lower speed with the tighter CAS latency if the higher speed gives a higher overall latency.

For example:
Looking at the table you still see a latency rise with the example of CAS 5 at 1000 is slightly faster than than CAS 6 at 1150 which is slightly faster than CAS 7 at 1333, things change though at DDR1600 where CAS 8 is as fast as cas5 at 1000 so you need to examine what is actually faster and tune your system accordingly.

The extended table:

Its know some of the new DDR3 modules are hitting DDR1680, so I extended the table to 1667 so you can see where the CAS latency will fall. CAS 7 will be near impossible at 1667 but CAS 8 looks to be a possibility with 9.6ns it looks faster than CAS 5 at 1000


Remember we have not looked at the effects of TRCD and TRP yet, this is just the CAS latency but it gives you an idea of how speed scales with latency timing increases.